The present disclosure relates to semiconductor memory devices, and more particularly, to a semiconductor memory device which achieves high-speed operation while reducing or preventing data destruction in a non-selected memory cell during data write operation.
In conventional static random access memory (SRAM) devices, the further miniaturization of transistors included in a memory cell would increase significant variations in transistor characteristics, disadvantageously leading to destruction of data stored by the memory cell during memory operation.
There is a technique of reducing or preventing data destruction during read operation in which bit lines are provided for write operation and read operation separately. There is also a technique of reducing or preventing data destruction in a non-selected memory cell during write operation in which data read from the non-selected memory cell is written back to the non-selected memory cell (see Japanese Patent Publication No. 2007-4888 and International Publication No. 2008/032549).
There are the following problems with the above conventional technique of reducing or preventing data destruction during write operation in a semiconductor memory device.
Firstly, data which has once been read is written back to a non-selected memory cell during write operation. Therefore, the operation time is longer than that of simple write or read operation, and therefore, the speed of the operation of the SRAM device disadvantageously cannot be increased.
Next, in order to achieve the data write-back operation, a write circuit having a capability similar to that of a write buffer used in conventional write operation is required. Also, the timing of writing back needs to be accurately controlled, and therefore, the number of parts increases, disadvantageously resulting in an increase in the circuit area of the SRAM device.